Deep-submicron scaling required for VLSI systems dominates design considerations in the microelectronics industry. As gate electrode length is scaled down, the source and drain junctions must be scaled down accordingly to suppress the so-called short channel effects (SCE) that degrade the performance of miniaturized devices. A major problem related to complementary metal oxide silicon (CMOS) scaling is the undesirable increase in parasitic resistance. As the source/drain junction depth and polycrystalline silicon line width are scaled into the deep-submicron range, contact resistance becomes more significant and needs to be reduced.
The principle way of reducing contact resistances between polysilicon gates and source/drain regions and interconnect lines is by forming metal silicides atop the source/drain regions and the gate electrodes prior to application of the conductive film for formation of the various conductive interconnect lines. Silicide regions are typically formed using a salicide (self-aligned silicide) process. In the salicide process, a thin layer of metal is blanket deposited over the semiconductor substrate, specifically over exposed source/drain and gate electrode regions. The wafer is then subjected to one or more annealing steps. This annealing process causes the metal to selectively react with the exposed silicon of the source/drain regions and the gate electrodes, thereby forming a metal silicide. The process is referred to as a self-aligned silicidation process because the silicide layer is formed only where the metal material directly contacts the silicon source/drain regions and the polycrystalline silicon (polysilicon) gate electrode. Following the formation of the silicide layer, the un-reacted metal is removed and an interconnect process is performed to provide conductive paths, such as by forming via holes through a deposited interlayer dielectric and filling the via holes with a conductive material, e.g., tungsten.
The conventional silicidation process, however, suffers drawbacks when the integrated circuit formation technology evolves to 65 nm and below. An example of the problem is illustrated in FIG. 1, which includes slim spacers 2 that are widely used for lowering sheet resistance in LDD regions and for applying greater stress to the channel region. The formation process for the MOS device shown in FIG. 1 includes forming LDD regions 6, forming thick spacers, forming deep source/drain regions 8, and thinning the thick spacers to form slim spacers 2. Silicide regions 4 are then formed aligned with the slim spacers 2. Such a process may result in silicide regions 4 intruding into LDD regions 6. In 65 nm technology and below, LDD regions 6 are shallow, for example, with a depth of 100 Å to about 150 Å. Typical silicide regions, however, have a thickness of about 170 Å, which is greater than the depth of LDD regions 6. Silicide regions 4 thus punch through the junctions between the respective LDD regions and the substrate, resulting in significant leakage current.
Accordingly, what is needed in the art is a new method and structure that may incorporate silicides to take advantage of the benefits associated with reduced resistivity while at the same time overcoming the deficiencies of the prior art.